← Work
Built from original work · Browser reinterpretation
An oscilloscope,
from the circuit up.
FPGA acquisition, a custom serial protocol, and a Qt host, reimplemented as an interactive signal bench anyone can open.
- VHDL
- C++ / Qt
- Angular
- WebAssembly
01FPGAsample · buffer · trigger
→02Serialframe · transfer · inspect
→03Hostrender · measure · explore

The original acquisition board, probes, and test signal.

A custom board built around the FPGA module and analog connectors.
Live bench · deterministic signal
Touch the signal.
Loading compute core
- Frequency
- 2.4 kHz
- Period
- 417 µs
- Peak to peak
- 3.60 V
- RMS
- 1.27 V
Under the hood
One project.
Three layers.
Acquisition close to the metal.
VHDL logic coordinates sampling, ADC data, DMA behavior, and the memory-mapped system.
A small language for the board.
Serial peek, poke, version, firmware, and sample commands connect low-level state to the host.
Complex behavior, calm controls.
The original Qt host handled connection, updates, triggering, smoothing, snapshots, and display.